Clock Network Synthesis with Concurrent Gate Insertion

In VLSI digital circuits, clock network plays an important role on the total performance of the chip. Clock skew and power dissipation are two major focuses of concerns in the clock network synthesis. During topology generation, the locations of buffer and gate insertion are usually not available. Despite local optimization, the global performance is limited. In this paper, a novel approach of topology generation with concurrent gate insertion is proposed. Meanwhile, a strict clock slew constraint is applied with comprehensive buffer insertion techniques. By clock gating, the switched capacitance of the clock tree is reduced, with acceptable extra cost caused in controller tree. In experimental results it is shown that our approach has good performance on the reduction of both clock skew and power dissipation.